1. Introduction
This invention relates to the familiar problem of protecting components such as field effect transistors (FET's) from excessive voltages that may be caused, for example, by an electrostatic discharge (ESD). Protection circuits are important for CMOS devices because as their dimensions are made smaller, they become more susceptible to damage by ESD.
This protection circuit uses a silicon controlled rectifier (SCR), and it will be helpful to review the features and terminology of SCRs that particularly apply to this invention. An SCR can be represented in a circuit diagram as an NPN bipolar junction transistor and a PNP bipolar junction transistor that are interconnected so that each receives base current from collector terminal of the other. When either transistor is turned on, it supplies base current to the other. Thus the circuit latches with both transistors turned on after either of the transistors is initially turned on. The two transistors turn off when the current is interrupted in either transistor.
2. The Prior Art
Chatterjee and Polgreen have discussed the advantages of an SCR as a protection device in a paper in the IEEE 1990 Symposium on VLSI Technology, pages 75-76, entitled "A Low-Voltage Triggering SCR for ON-Chip ESD Protection at Output and Input Pads". FIG. 2 shows the structure of an integrated circuit device with an SCR and an FET for triggering the SCR at a low voltage.
Rountree, IEDM Tech Dig pp 580-583 "ESD Protection for Submicron CMOS Circuits Issues and Solutions" has also discussed protection circuits using SCR's.
Avery U.S. Pat. No. 4,484,244 teaches a protection circuit having two SCR's connected to a protected line. One SCR (Q1, Q2) conducts excessive positive voltages to ground and the other (Q3, Q4) conducts excessive negative voltages to ground.
Avery U.S. Pat. No. 4,595,941 show an FET connected to turn on an SCR in response to an excessive voltage.